Security characterization of a risc-v processor h/f

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Les 20 000 collaboratrices et collaborateurs du CEA partagent trois valeurs fondamentales :

- La conscience des responsabilités
- La coopération
- La curiosité With the rise of new development models based on open source, secure hardware components are increasingly being developed in public implementations, notably within the OpenHW Group [1]. The possibility of building a complete system from publicly available, open-source components is becoming a reality. For example, the CV32E40S RISC-V processor [2], derived from the CV32E40P [3], incorporates several hardware countermeasures against fault injection and side-channel attacks. However, a significant challenge lies in evaluating both the security level of each individual countermeasure and the overall effectiveness of these countermeasures when combined.
In [4], we introduced a method dedicated to the formal modeling and verification of microarchitecture-level fault injections and their effects on complex hardware/software systems. In the proposed internship, we are looking to apply this methodology to the CV32E40S processor, and to evaluate the potential security gap with regards to real hardware attacks. A security characterization of the CV32E40S will BE performed using affordable fault injection equipment such as the ChipWhisperer fault injection tools [5].
The main tasks carried out in this internship will BE :
Implement the CV32E40S on an FPGA and functionally validate the attack setup using ChipWhisperer fault injection tools [5].
Define attack scenarios and characterize vulnerabilities using the uArchiFI formal tool [4]
Exploit the defined attack scenarios to perform a comprehensive security characterization of the CV32E40S using ChipWhisperer fault injection tools.

[1] OpenHW Group. https://www.openhwgroup.org
[2] Processor RISC-V CV32E40S. https://github.com/openhwgroup/cv32e40s
[3] Processor RISC-V CV32E40P. https://github.com/openhwgroup/cv32e40p
[4] µArchiFI : Formal Modeling and Verification Strategies for Microarchitectural Fault Injections. S. Tollec, M. Asavoae, D. Couroussé, K. Heydemann, et M. Jan. in FMCAD. 2023 https://doi.org/10.34727/2023/isbn.978-3-85448-060-0_18
[5] https://www.newae.com/